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Final Electrical Specifications
LTC1642 Hot Swap Controller
May 1999
FEATURES
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DESCRIPTIO
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Single Channel Positive NFET Driver Programmable Undervoltage and Overvoltage Protection Foldback Current Limit Adjustable Current Limit Time-Out Latch Off or Automatic Retry on Current Fault Driver for SCR Crowbar on Overvoltage Programmable Reset Timer Reference Output with Uncommitted Comparator VCC: 2.97V to 16.5V Normal Operation, Protected Against Surges to 33V. 16-Pin SSOP Package
The LTC(R)1642 is a 16-pin Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, the board supply voltage can be ramped up at a programmable rate. A high side switch driver controls the N-channel gate for supply voltages ranging from 2.97V to 16.5V. The SENSE pin allows foldback limiting of the load current, with circuit breaker action after a programmable delay time. The delay allows the part to power-up in current limit. The CRWBR output can be used to trigger an SCR for crowbar load protection after a programmable delay if the input supply exceeds a programmable voltage. The RESET output can be used to generate a system reset with programmable delay when the supply voltage falls below a programmable voltage. The ON pin can be used to cycle the board power. The LTC1642 is available in the 16-pin SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
APPLICATIO S
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Hot Board Insertion Electronic Circuit Breaker
TYPICAL APPLICATIO
12V R5 110k 1% LATCH OFF: FLOAT FAULT AUTOMATIC RETRY: TIE FAULT TO ON
R1 0.010 5% C7 0.1F
Q1 FDR9410A
R2 100 5% 16 15 SENSE 14 GATE
R8 330 5% C1 0.047F RESET 5 7 1 12 Q2 2N2222 Q3 MCR 12DC
VCC 10 UNDERVOLTAGE = 10.8V R6 2.87k 1% OVERVOLTAGE = 13.2V R7 11.3k 1% D1 1N4148 4 6 9
COMPOUT ON FAULT OV LTC1642
FB CRWBR COMP-
11 COMP+ REF GND 8 C3 0.33F BRK TMR 2 RST TMR 3 C5 C2 0.1F 0.33F 13
RESET TIME = 200ms CURRENT LIMIT TIME = 20ms CROWBAR TIME = 90s
C6 0.01F
R9 REQUIRED ONLY WITH SENSITIVE GATE SCRs, NOT NEEDED WITH MCR12
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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12V AT 2.5A CLOAD R3 107k 1% POWER-GOOD = 11.4V R9 220 5% R4 13k 1%
1642 TA01
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LTC1642
ABSOLUTE
(Note 1)
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PACKAGE/ORDER I FOR ATIO
TOP VIEW CRWBR 1 BRK TMR 2 RST TMR 3 ON 4 RESET 5 FAULT 6 FB 7 GND 8 16 VCC 15 SENSE 14 GATE 13 REF 12 COMP - 11 COMP + 10 COMPOUT 9 OV
Supply Voltage (VCC) .................................- 0.3V to 33V SENSE Pin ................................... - 0.3V to (VCC + 0.3V) GATE Pin ...................................................- 0.3V to 27V All Other Pins ..........................................- 0.3V to 16.5V Operating Temperature Range LTC1642C ............................................... 0C to 70C LTC1642I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1642CGN LTC1642IGN
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150C, JA = 130C/W
Consult factory for Military grade parts.
DC ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V unless otherwise specified.
SYMBOL ICC VLKHI VLKLO VLKHYST VCC VFB VFB VFBHST VOV VOV VOVHYST VRST VRST IRST VBRK VBRK IBRK VCR VCR ICR PARAMETER VCC Supply Current VCC Undervoltage Lockout (Low to High) VCC Undervoltage Lockout (High to Low) VCC Undervoltage Lockout Hysteresis Operating Voltage Range FB Pin Voltage Threshold (FB Falling) FB Pin Threshold Line Regulation FB Pin Voltage Threshold Hysteresis OV Pin Voltage Threshold (OV Rising) OV Pin Threshold Line Regulation OV Pin Voltage Theshold Hysteresis RST TMR Pin Voltage Threshold (RST TMR Rising) RST TMR Pin Threshold Line Regulation RST TMR Pin Current BRK TMR Pin Voltage Threshold (BRK TMR Rising) BRK TMR Pin Threshold Line Regulation BRK TMR Pin Current CRWBR Pin Voltage Theshold CRWBR Pin Threshold Line Regulation CRWBR Pin Current 2.97V VCC 16.5V CRWBR On, VCRWBR = 0V CRWBR On, VCRWBR = 2.1V CRWBR Off, VCRWBR = 1.5V 2.97V VCC 16.5V Timer On Timer Off, VBRKTMR = 1.5V 2.97V VCC 16.5V Timer On Timer Off, VRSTTMR = 1.5V
q q q q q q q q q q q q
CONDITIONS ON = VCC
q q q
MIN 2.55 2.35 2.97 1.208
TYP 1.25 2.73 2.50 230
MAX 3.0 2.95 2.80 16.5
UNITS mA V V mV V V mV mV V mV mV V mV A mA V mV A mA mV mV A A mA
1.220 5 3
1.232 15 1.232 15 1.250 15 -1.5 1.250 15 -15 425 15 - 30 -1000
2.97V VCC 16.5V
q
1.208
1.220 5 3
2.97V VCC 16.5V
q
1.200 - 2.5 1.200 - 30 375 - 60
1.220 5 -2.0 10 1.220 5 -20 10 410 4 - 45 -1500 2.3
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LTC1642
DC ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V unless otherwise specified.
SYMBOL VCB ICP VGATE PARAMETER Circuit Breaker Trip Voltage GATE Pin Output Current External N-Channel Gate Drive CONDITIONS VCB = (VCC - VSENSE), VFB = GND VCB = (VCC - VSENSE), VFB = 1V Charge Pump On, VGATE = GND Charge Pump Off, VGATE = 5V VGATE - VCC, VCC = 3V VGATE - VCC, VCC = 5V VGATE - VCC, VCC = 15V
q q q q q q
MIN 15 45 - 30 4.5 10 4.5 1.30
q
TYP 25 52.5 - 25 10 5.9 11.5 8.5 1.34 1.22 110
MAX 36 60 - 20 8.0 14 18 1.38 1.26 0.4
UNITS mV mV A mA V V V V V mV V A V mV mV mA mV mV
VONHI VONLO VONHYST VOL IPU VREF VLNR VLDR IRSC VCOS VCHYST
ON Pin Threshold (Low to High) ON Pin Threshold (High to Low) ON Pin Hysteresis Output Low Voltage Logic Output Pull-Up Current Reference Output Voltage Reference Line Regulation Reference Load Regulation Reference Short-Circuit Current Comparator Offset Voltage Comparator Hysteresis RESET, FAULT, COMPOUT IO = 1.5mA RESET, FAULT = GND No Load 2.97V VCC 16.5V, No Load IO = 0mA to -1mA, Sourcing Only VREF = 0V VCM = VREF VCM = VREF
q q q q q
1.20
- 15 1.208 1.220 5 2.5 4.5 10 3 1.232 15 7.5
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
PI FU CTIO S
CRWBR (Pin 1): Combination Overvoltage Timer and Crowbar Circuit Trigger. The timer sets the overvoltage time needed to trigger the crowbar circuit. To use the timer connect a capacitor C to ground; the trigger time is 9ms*C(F). When the timer is off an internal N-channel pulls the pin to ground. The timer is started when the OV comparator trips. A 45A current source is connected from VCC to the CRWBR pin, and the voltage increases at a rate of 45/C(F) Volts/second. When the voltage reaches 410mV the current sourced by the pin increases to 1.5mA. Boost this current with an NPN emitter follower to trigger a crowbar SCR. BRK TMR (Pin 2): Analog Timer which Limits the Time the Part Remains In Current Limit. To use the timer connect a capacitor from BRK TMR to ground. BRK TMR is pulled to ground until the sense resistor current reaches its limit, when the pin begins sourcing 20A and the pin voltage increases at a rate of 20/C(F) Volts/second. When the pin reaches 1.23V the GATE pin is pulled to ground and the FAULT output is asserted until the chip is reset. To allow the part to remain in current limit indefinitely ground BRK TMR. RST TMR (Pin 3): Analog System Timer. To use the timer connect a capacitor from RST TMR to ground. This timer sets the delay from the ON pin going high to the start of the GATE pin's ramp; it also sets the delay from output voltage good, as sensed by the FB pin, to RESET going high. When the timer is off, an internal N-channel shorts RST TMR to ground. When the timer is turned on a 2A current from VCC is connected and the RST TMR pin voltage starts to ramp up at a rate of 2/C(F) Volts/second. The timer trips when the voltage reaches 1.23V.
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LTC1642
PI FU CTIO S
ON (Pin 4): Control. When ON is low the GATE pin is grounded and FAULT goes high. The GATE pin voltage starts ramping up one RST TMR timing cycle after ON goes high. Pulsing the ON pin low for at least 2s also resets the chip when it latches off after a sustained overvoltage or current limit. The threshold on a low to high transition is 1.34V with 110mV of hysteresis. RESET (Pin 5): Open Drain Output. RESET is pulled low if the voltage at the FB pin is below its trip point and goes high one timing cycle after the FB voltage exceeds its trip point plus 3mV of hysteresis. RESET has a weak pull-up to one diode drop below VCC; an external resistor can pull the pin above VCC. FAULT (Pin 6): Open Drain Output. FAULT is pulled low when the part latches itself off following a sustained overvoltage or current limit. It goes high 2s after the ON pin goes low. FAULT has a weak pull-up to one diode drop below VCC; an external resistor can pull the pin above VCC. FB (Pin 7): Noninverting Input to An Analog Comparator; the inverting input is tied to the 1.23V internal reference. The FB comparator can be used with an external resistive divider to monitor the output supply voltage. When the FB voltage is lower than 1.23V the RESET pin is pulled low. RESET goes high one system timing cycle after the voltage at FB exceeds its threshold by 3mV of hysteresis. A low pass filter at the comparator's output prevents negative voltage glitches from triggering a false reset. GND (Pin 8): Chip Ground. OV (Pin 9): Analog Input Used to Monitor Overvoltages. When the voltage on OV exceeds its trip point the GATE pin is pulled low immediately and the CRWBR timer starts. If OV remains above its trip point (minus 3mV of hysteresis) long enough for CRWBR to reach its trip point the part latches off until reset by pulsing the ON pin low; otherwise, the GATE pin begins ramping up one RST TMR timing cycle after OV goes below its trip point. COMPOUT (Pin 10): Uncommitted Comparator's Open Drain Output. COMP + (Pin 11): Uncommitted Comparator's Noninverting Input. COMP - (Pin 12): Uncommitted Comparator's Inverting Input. REF (Pin 13): The Reference Voltage Output, 1.232V 2%. To ensure stability the pin should be bypassed with a 0.1F compensation capacitor. For VCC = 5V it can source 1mA. GATE (Pin 14): High Side Gate Drive for the External N-Channel. An internal charge pump provides at least 4.5V of gate drive, but can only source 25A. The pin requires an external series RC network to ground to compensate the current limit loop, and to limit the maximum voltage ramp which is dV/dt (V/s) = 25/C(F). GATE is immediately pulled to ground when the overvoltage comparator trips or the input supply is below the undervoltage lockout trip point. During current limit the GATE voltage is adjusted to maintain constant load current until the BRK TMR pin trips, when the pin is pulled to ground until the chip is reset. SENSE (Pin 15): Current Limit Set. To use the current limit place a sense resistor in the supply path between VCC and SENSE. Should the drop across the resistor exceed a threshold voltage the GATE pin is adjusted to maintain a constant load current and the timer at the BRK TMR pin is started. To protect the external FET from thermal damage the circuit breaker trips after the BRK TMR timing cycle. A foldback feature makes the current limit decrease as the voltage at FB approaches ground. Figure 3 quantifies the relationship. To disable the current limit short SENSE to VCC. VCC (Pin 16): Positive Supply Voltage; between 2.97V and 16.5V in normal operation. An internal undervoltage lockout circuit holds the GATE pin at ground until VCC exceeds 2.73V. If VCC exceeds 16.5V an internal shunt regulator protects the chip from VCC and SENSE pin voltages up to 33V. When the internal shunt regulator is active and the charge pump is on the GATE pin voltage will usually be low but this is not guaranteed; use the OV pin to ensure that the pass device is off. The VCC pin also provides a Kelvin connection to the high side of the SENSE resistor.
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LTC1642
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When a circuit board is inserted into a live backplane its supply bypass capacitors can draw large currents from the backplane power bus as they charge. These currents can permanently damage connector pins and can glitch the backplane supply, resetting other boards in the system. The LTC1642 limits the charging currents drawn by a board's capacitors, allowing safe insertion in a live backplane. Power Supply Ramping In the circuit shown in Figure 1 the LTC1642 and the external N-channel pass transistor Q1 work together to limit charging currents. When power is first applied to VCC the chip holds Q1's gate at ground. After a programmable delay a 25A current source begins to charge the external capacitor C2, generating a voltage ramp of 25A/C2 V/s at the GATE pin. Because Q1 acts as a source follower while its gate ramps, the current charging the board's bypass capacitance CLOAD is limited to 25A*CLOAD/C2. An internal charge pump supplies the 25A gate current, ensuring sufficient gate drive to Q1. At 3V VCC the minimum gate drive is 4.5V; at 5V VCC the minimum is 10V; at 15V VCC the minimum is again 4.5V, due to a Zener clamp from the GATE pin to ground. Resistor R3 limits this Zener's transient current during board insertion and removal and protects against high frequency FET oscillations. R2 Q1
VIN 12V 2.5A C7 0.1F R1 10k 4 0.010 16 VCC ON 15 SENSE GATE 14 R4 330 C2 0.047F 5 FDR9410A
VOLTS
+
R3 100
LTC1642
2
BRK TMR RST TMR
RESET GND 8
C4 0.33F
C1 0.33F
3
ALL RESISTORS 5% UNLESS NOTED RESET DELAY = 200ms SHORT-CIRCUIT DURATION = 20ms
Figure 1. Supply Control Circuitry
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The delay before the GATE pin voltage begins ramping is determined by the system timer. It comprises an external capacitor C1 from the RST TMR pin to ground; an internal 2A current source feeding RST TMR from VCC; an internal comparator, with the positive input tied to RST TMR and the negative input tied to the 1.23V reference; and an NMOS pull-down. In standby, the NMOS holds RST TMR at ground; when the timer starts the NMOS turns off and the RST TMR voltage ramps up as the current source charges the capacitor. When RST TMR reaches 1.23V the timer comparator trips; the GATE voltage begins ramping and RST TMR returns to ground. The ramp time t needed to trip the comparator is : t(ms) = 615*C1(F).
VIN RST TMR GATE SLOPE = 25A/C(V/s) VOUT TIME
1642 F02
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Figure 2. Supply Control Timing
Powering-Up In Current Limit Ramping the GATE pin voltage indirectly limits the charging current to I = 25A*CLOAD/C2, where C2 is the external capacitor connected to the GATE and CLOAD is the load capacitance. If the value of CLOAD is uncertain, then a worst-case design can often result in needlessly long ramp times, and it may be better to limit the charging current directly. Current Limiting and Solid-State Circuit Breaker The board current can be limited by connecting a sense resistor between the LTC1642's VCC and SENSE pins. An internal servo loop adjusts the GATE pin voltage such that Q1 acts as a constant current source if the voltage drop across the sense resistor reaches a limit. The voltage limit across the sense resistor increases as the output charges
VOUT CLOAD
1642 F01
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LTC1642
APPLICATIO S I FOR ATIO
up; this "foldback" limiting tends to keep the power dissipation in the N-channel pass transistor constant. The output voltage is sensed at the FB pin. The limiting sense resistor voltage is 23mV when FB is grounded, but increases gradually to 53mV when FB exceeds 1V; Figure 3 shows the full dependence. When the sense resistor voltage reaches its limit, a circuit breaker timer starts. This timer uses the BRK TMR pin and has a 1.23V threshold. If BRK TMR reaches 1.23V the timer comparator trips, tripping the circuit breaker; if the sense resistor voltage falls below its limit before the comparator trips the GATE voltage begins ramping back up immediately. The ramp time t needed to trip the comparator is t(ms) = 62*C(F), where C is the external capacitance. Once the circuit breaker trips, GATE and FAULT remain at ground until the chip is restarted. To restart, hold the ON pin low for at least 2s and FAULT will go high. Then take ON high again and the GATE will ramp up after a system timing cycle. Or, configure the LTC1642 to restart itself after the circuit breaker trips by connecting FAULT to the ON pin.
MAXIMUM SENSE RESISTOR VOLTAGE (mV)
70 60
50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 FB PIN VOLTAGE (mV)
1642 F03
Figure 3. Maximum Sense Resistor Voltage vs FB Voltage
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The servo loop controlling Q1 during current limit has a unity-gain frequency of about 125kHz; in Figure 1 R4, together with C2, provide compensation. To ensure stability the product 1/(2**R4*C2) should be kept below the unity-gain frequency, and C2 should be more than Q1's gate-source capacitance. The values shown in Figure 1, 0.047F and 330, are a starting point. Typical waveforms during a load short to ground are shown in Figure 4. The load is shorted to ground at time 1. The GATE voltage drops until the load current equals its maximum limit, and the circuit breaker timer starts. The short is cleared at time 2, before the timer trips. The BRK TMR pin returns to ground, and the GATE voltage begins ramping up. At time 3 the load is shorted again and at time 4 the timer trips, pulling the GATE to ground and asserting FAULT. Although the short is cleared at time 5, FAULT doesn't go high until the ON pin is pulled low at time 6. At time 7 ON goes high and the system timer starts. When it trips at time 8 the GATE voltage begins ramping.
6 1 ILOAD 2 3 45 7 8 ILIMIT 0A GATE VOUT GATE BRK TMR 1.23V FAULT ON RST TMR 1.23V
1642 F04
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Figure 4. Current Limit and Circuit Breaker Timing
LTC1642
APPLICATIO S I FOR ATIO
Automatic Restart After a Current Fault
The LTC1642 will automatically attempt to restart itself after the circuit breaker opens if the FAULT output is tied to the ON pin. The circuit is shown in Figure 5, and the waveforms during a load short in Figure 6. During a continuous current limit such as a load short, the N-channel pass transistor's duty cycle is equal to the circuit breaker timer period, divided by the sum of the circuit breaker and system timer periods. If FAULT is tied to ON then open drain logic should be used to drive the
VIN 12V 2.5A C7 0.1F R1 4 6 R2 0.010 16 VCC ON 15 SENSE GATE 14 R4 330 C2 0.047F 1 Q2 2N2222 Q3 MCR 12DC Q1 FDR9410A VOUT CLOAD
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R3 100
FAULT LTC1642 9 OV 2 R5 C4 0.33F BRK TMR RST TMR 3 C1 0.33F CRWBR GND 8
C5
1642 F05
ALL RESISTORS 5% UNLESS NOTED C4 SHORT-CIRCUIT DUTY CYCLE = = 9% C4 + 10 * C1
Figure 5. Automatic Restart Circuit
VIN 12V 2.5A R2 0.010 C7 0.1F 16 VCC 15 SENSE
UNDERVOLTAGE LOCKOUT THRESHOLD = 10.7V
ALL RESISTORS 5% UNLESS NOTED
Figure 7. Setting a Higher Undervoltage Lockout
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node. The external pull-up resistor at the ON pin may be omitted because FAULT provides a weak pull-up. Undervoltage Lockout An internal undervoltage lockout circuit holds the charge pump off until VCC exceeds 2.73V. If VCC falls below 2.5V, it turns off the charge pump and clears overvoltage and current limit faults. For higher lockout thresholds tie the ON pin to a resistor divider driven from VCC, as shown in Figure 7. This circuit keeps the charge pump off until VCC exceeds (1+R1/R5)*1.34V, and also turns it off if VCC falls below (1+R1/R5)*1.23V.
1 GATE 2 3 4 5 6 VOUT BRK TMR 1.23V ON/FAULT RST TMR 1.23V
1642 F06
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Figure 6. Automatic Retry Following a Load Short
Q1 FDR9410A
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R3 100 14
VOUT CLOAD
R1 464k 1% 4
LTC1642 ON GATE
C2 0.047F R5 60.4k 1% RST TMR 3 C1 0.33F GND 8 R4 330
1642 F07
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LTC1642
APPLICATIO S I FOR ATIO
Overvoltage Protection
The LTC1642 can protect a load from overvoltages by turning off the pass transistor if the supply voltage exceeds a programmable limit, and by triggering a crowbar SCR if the overvoltage lasts longer than a programmable time. The part can also be configured to automatically restart when the overvoltage clears. The overvoltage protection circuitry is shown in Figure 8. The external components comprise a resistor divider driving the OV pin, timing capacitor C5, NPN emitter follower Q2, and crowbar SCR Q3. Because the MCR12DC is not a sensitive-gate device, the optional resistor shunting the SCR gate to ground is omitted. The internal components comprise a comparator, 1.23V bandgap reference, two current sources, and a timer at the CRWBR pin. When VCC exceeds (1+R1/R5)*1.23V the comparator's output is high and internal logic pulls the GATE down and starts the timer. This timer has a 0.410V threshold and uses the CRWBR pin; when CRWBR reaches 0.410V the timer comparator trips, and the current sourced from VCC increases to 1.5mA. Emitter follower Q2 boosts this current to trigger crowbar SCR Q3. The ramp time t needed to trip the comparator is : t(ms) = 9.1*C5(F). Once the CRWBR timer trips the LTC1642 latches off: after the overvoltage clears GATE and FAULT remain at ground and CRWBR continues sourcing 1.5mA. To restart the part after the overvoltage clears, hold the ON pin low for at least 2s and then bring it high. The GATE voltage will begin ramping up one system timing cycle later. The part will restart itself if FAULT and ON are connected: GATE begins ramping up one system timing cycle after the overvoltage clears. Figure 9 shows typical waveforms when the divider is driven from VCC. The OV comparator goes high at time 1, causing the chip to pull the GATE pin to ground and start the CRWBR timer. At time 2, before the timer's comparator trips, OV falls below its threshold; the timer resets and GATE begins charging one system timing cycle later at time 3. Another overvoltage begins at time 4, and at time 5 the CRWBR timer trips; FAULT goes low and the CRWBR pin begins sourcing 1.5mA. Even after OV falls below 1.23V at time 6, GATE and FAULT stay low, and CRWBR continues to source 1.5mA. FAULT goes high when ON
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VIN 12V 2.5A R2 0.010 R1 127k 1% 16 VCC OV GATE 15 SENSE 14 R4 330 C2 0.047F Q2 2N2222 CRWBR GND 8 1 Q1 FDR9410A C7 0.1F
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R3 100
VOUT CLOAD
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R5 12.4k 1%
LTC1642
4 6
ON FAULT RST TMR 3 C1 0.33F
Q3 MCR12DC
C5 0.01F
ALL RESISTORS 5% UNLESS NOTED OV COMPARATOR TRIPS AT VIN = 13.85V RESET TIME = 200ms CROWBAR DELAY TIME = 90s
1642 F08
Figure 8. Overvoltage Protection Circuitry
1 VCC 0V OV 1.23V 0V 2 3 4 567 8
GATE
0V
VOUT VCC
0.41V CRWBR 1.23V
RST TMR
ON
FAULT
1642 F09
Figure 9. Overvoltage Timing (High Side)
LTC1642
APPLICATIO S I FOR ATIO
goes low at time 7, and GATE begins charging at time 8, one RST TMR cycle after FAULT goes high. Figure 10 shows typical waveforms when the OV divider is driven from the N-channel's low side. Because the voltage driving the divider collapses after the OV comparator trips, FAULT stays high and CRWBR stays near ground, which prevents the pin from triggering an SCR. The GATE voltage begins ramping up after a RST TMR timing cycle. Automatic Restart If there is an overvoltage, and the resistor divider feeding OV is connected to the output of the N-channel pass transistor, the LTC1642 will automatically restart even if FAULT is not tied to ON. If the divider is connected to the input side, the LTC1642 will restart itself only if FAULT is tied to ON, and only after the overvoltage clears.
1 VCC
2
3
4
5
67
OV COMPARATOR PROPAGATION DELAY (s)
0V 1.23V OV 0V
GATE VOUT CRWBR RST TMR 0.41V
1.23V
FAULT
1642 F10
0V
Figure 10. Overvoltage Timing (Low Side)
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The OV and FB Comparators The propagation delay through the OV and FB comparators on low to high transitions depends strongly on the differential input voltage. The relationship is shown in Figure 11. The minimum propagation delay for large overdrives is about 20s. In addition the comparators have 3mV of hysteresis. Internal Voltage Clamp Protection The LTC1642 includes a shunt regulator to protect itself from VCC and SENSE pin voltages up to 33V. The regulator turns on when VCC exceeds 16.5V and limits most of the chip's circuitry to 15V. When it is on the chip functions normally with one exception: if the charge pump is on, the GATE voltage is usually near ground but this is not guaranteed. Use the OV pin to ensure that GATE is grounded. The pull-up voltage on the RESET and FAULT pins follows VCC until the shunt regulator turns on. When the regulator is on the pull-up voltage is 14.4V.
70 60 50 40 30 20 10 0 0 40 80 120 160 OV OVERDRIVE (mV) 200 240
1642 F11
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Figure 11. OV Comparator Propagation Delay vs Overdrive Voltage
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LTC1642
APPLICATIO S I FOR ATIO
Undervoltage Monitor
The LTC1642 will assert RESET if a monitored voltage falls below a programmable minimum. When the monitored voltage has exceeded its minimum for at least one system timing cycle, RESET goes high. The monitoring circuitry comprises an internal 1.23V bandgap reference, an internal precision voltage comparator and an external resistive divider to monitor the output supply voltage. The circuit is shown in Figure 12, and typical waveforms in Figure 13. When the voltage at the FB pin rises above its reset threshold (1.23V), the comparator output goes low and a timing cycle starts (times 1 and 5). Following the cycle RESET is pulled high. At time 2 the voltage at FB drops below the comparator's threshold and RESET is pulled low. If the FB pin rises above the reset threshold for less than a timing cycle the RESET output will remain low (time 3 to time 4). The 15A pull-up current source to VCC on RESET has a series diode so the pin can be pulled above VCC by an external pull-up resistor without forcing current back into the supply. Reference The LTC1642's internal voltage reference is buffered and brought out to the REF pin. The buffer amplifier should be compensated with a capacitor connected between REF and ground. If no DC current is drawn from REF, 0.1F ensures an adequate phase margin, but the minimum compensation increases if REF sources a substantial DC current, as shown in Figure 14. Uncommitted Comparator The uncommitted comparator has an open drain output. The comparator has 3mV of hysteresis: the output goes high when the differential input voltage exceeds 1.5mV and goes low when the differential input is less than -1.5mV.
MINIMUM REF COMPENSATION (F)
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VIN 12V 2.5A R2 0.010 16 VCC 4 ON 15 SENSE GATE 14 R4 330 C2 0.047F FB 7 R6 12.4k 1% 5 R7 95.3k 1% Q1 FDR9410A
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VOUT CLOAD
LTC1642
RESET RST TMR GND C1 0.33F 3 8
1642 F12
ALL RESISTORS 5% UNLESS NOTED. FB COMPARATOR TRIPS AT VOUT = 10.7V
Figure 12. Undervoltage Monitoring Circuitry
1 V1 VOUT RST TMR
2 V2
3 V1
4 V2
5
V1
RESET
1642 F13
Figure 13. Supply Monitor Waveforms
10.0 4.0 2.0 1.0 0.4 0.2 0.1
100A
1mA REFERENCE CURRENT
10mA
1642 F14
Figure 14. Minimum REF Compensation vs REF Current
LTC1642
PACKAGE DESCRIPTIO
0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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Dimensions in inches (millimeters) unless otherwise noted.
GN Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
0.009 (0.229) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.015 0.004 x 45 (0.38 0.10) 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727)
23
4
56
7
8 0.004 - 0.0098 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.025 (0.635) BSC
GN16 (SSOP) 0398
11
LTC1642
TYPICAL APPLICATIO
R9 51
R10 12k C9 270pF
C8 15F 10V KEMET TANT
+
4 C7 0.1F
C14 2200pF
5V R5 36.5k 1% LATCH OFF: FLOAT FAULT AUTOMATIC RETRY: TIE FAULT TO ON C6 0.1F 16 VCC 3.3V POWER-GOOD = 3.00V UNDERVOLTAGE = 4.49V R6 2.55k 1% OVERVOLTAGE = 5.47V R7 11.3k 1% D3 1N4148 10 4 6 FAULT 9 OV GND 8 C3 0.33F BRK TMR 2 15 SENSE R3 32.4k 1% C1 47nF RESET COMPOUT ON U1 LTC1642 FB CRWBR 5 7 1 Q2 2N2222 Q3 MCR 12DC 5V POWER-GOOD = 4.75V
ALL RESISTORS 5% UNLESS OTHERWISE NOTED RESET TIME = 200ms CURRENT LIMIT TIME =20ms CROWBAR TIME = 90s
RELATED PARTS
PART NUMBER LTC1421 LTC1422 LT1640 LTC1643 DESCRIPTION Hot Swap Controller Hot Swap Controller Negative Voltage Hot Swap Controller PCI-Bus Hot Swap Controller COMMENTS Multiple Supplies Single Supply in SO-8 Negative High Voltage Supplies 3.3V, 5V, 12V, -12V Supplies for PCI Bus
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
5V To 3.3V Hot Swap Supply Using the LTC1430
D2 MBR0530T1 4 U2 LTC1430CS 7 8 5 6 PVCC2 G2 SHDN COMP PVCC1 G1 FB GND 2 1 4 3 5678 123 C15 0.1F L1 3.5H CDRH1273R5 5678 Q4 Si4412DY C16 330F 6.3V KEMET TANT
+
C17 330F 6.3V KEMET TANT
+
C13 1F
D1 MBRS130T3 Q5 Si4412DY C18 680pF
R11 16.5k 1% C10 330F 6.3V KEMET TANT R12 10.2k 1% C11 330F 6.3V KEMET TANT C12 330F 6.3V KEMET TANT
3.3V OUT AT 5A R13 17.4k 1%
+
+
+
123
R14 12.1k 1%
R1, 0.005
Q1 MTB50N06V
R2 100 14 GATE
R8 330
12 COMP- COMP
+ 11
13 REF RST TMR C4 3 C2 0.1F 0.33F
C5 0.01F
R4 13k 1%
1642 TA02
1642is, sn1642 LT/TP 0599 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1999

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